1. Field of the Invention
The present invention relates to a wiring structure that has a plurality of slit dummies in a wiring.
2. Description of the Related Art
Recently, copper is used as a wiring material to reduce the resistance of the wiring. The wiring with copper is typically fabricated by a damascene process.
The conventional damascene process is shown in FIG. 10.
A silicon nitride film 204 is formed on a semiconductor substrate 202 and a silicon oxide film 206 is formed on the silicon nitride film 204 as shown in FIG. 10(A). Grooves 208a and 208b are formed in the silicon oxide film 206 as shown in FIG. 10(B). Then, a copper layer is formed on the silicon oxide layer 206 including the groove as shown in FIG. 10(C). Since the copper layer is formed, the groove is embedded by the copper layer. The copper layer on the insulating layer is removed by CMP (Chemical Mechanical Polishing) process as shown in FIG. 10(D). That is the copper layer is only remained in the grooves, and the remaining copper layer is used as the wiring. Because copper has a high diffusion rate in some dielectrics, particularly silicon dioxide, some form of barrier layer between the insulating layer and copper layer is required. Various barrier materials have been proposed including refractory metals such as titanium (Ti), tantalum (Ta).
The damascene process has a problem that a thickness of the wiring is reduced during the CMP process.
As shown in FIG. 10(D), a concave portion called dishing is formed in the surface of the wiring. The FIG. 10(D) shows a cross-section at the width direction of the wiring. A depth D of a portion that is deepest at the dishing is increased, while the width of the wiring is increased.
FIG. 2 is a plot of an experimental data that shows a relationship between the width of the wiring W and a variation of a sheet resistance ΔR. In FIG. 2, a horizontal axis is the width of the wiring W μm and a vertical axis is the variation of the sheet resistance ΔR %, while a height of the wiring is 500 nm. According to the plot, the ΔR is 5 or 6% when the W is 2 μm, the ΔR is 20% when the W is 10 μm and the ΔR is 25% or more when the W is 20 μm. That is, while the width of the wiring is increased, a difference between an actual resistance of the wiring and a resistance in design is increased.
In order to solve above problem, (1) a reference width is defined and (2) when a width of the wiring exceed the reference width, slit dummies are used.
The slit dummies are formed in the wiring to prevent the dishing. The slit dummies are used a different material from the wiring. The slit dummies are fabricated at the step of forming the grooves as shown in FIG. 10(B). During the grooves are formed in the silicon oxide film 206 by etching the silicon oxide film 206, the slit dummies are also formed in the silicon oxide film 206 by etching. That is, the slit dummies are made from the material to the silicon oxide film 206.
FIG. 11 is a schematic diagram of a conventional wiring structure with slit dummies.
The copper wiring 222 is formed in the silicon oxide film 216 and a bottom of the copper wiring 222 is formed on a silicon nitride film 218. Slit dummies 214 are formed in the copper wiring. Heights of the slit dummies 214 are equal to a height of the copper wiring 222. However, there is no clear standard in a length Dw and a length Dd of the slit dummy. Therefore, since too many slit dummies are formed in the wiring, a total width of the wiring is increased.
Accordingly, in an object of the present invention, a wiring structure for arranging slit dummies efficiently is provided.